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CY7C1370DV25 CY7C1372DV25
18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBLTM Architecture
Features
* Pin-compatible and functionally equivalent to ZBTTM * Supports 250-MHz bus operations with zero wait states -- Available speed grades are 250, 200 and 167 MHz * Internally self-timed output buffer control to eliminate the need to use asynchronous OE * Fully registered (inputs and outputs) for pipelined operation * Byte Write capability * Single 2.5V core power supply (VDD) * 2.5V I/O power supply (VDDQ) * Fast clock-to-output times -- 2.6 ns (for 250-MHz device) * Clock Enable (CEN) pin to suspend operation * Synchronous self-timed writes * Available in JEDEC-standard lead-free 100-Pin TQFP, lead-free and non-lead-free 119-Ball BGA and 165-Ball FBGA packages * IEEE 1149.1 JTAG-Compatible Boundary Scan * Burst capability--linear or interleaved burst order * "ZZ" Sleep Mode option and Stop Clock option
Functional Description
The CY7C1370DV25 and CY7C1372DV25 are 2.5V, 512K x 36 and 1 Mbit x 18 Synchronous pipelined burst SRAMs with No Bus LatencyTM (NoBLTM) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1370DV25 and CY7C1372DV25 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1370DV25 and CY7C1372DV25 are pin-compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects (BWa-BWd for CY7C1370DV25 and BWa-BWb for CY7C1372DV25) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.
Logic Block Diagram-CY7C1370DV25 (512K x 36)
A0, A1, A MODE
CLK CEN
ADDRESS REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC ADV/LD C
WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2
C
ADV/LD
BWa BWb BWc BWd
WE
WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC
WRITE DRIVERS
MEMORY ARRAY
S E N S E A M P S
O U T P U T R E G I S T E R S
D A T A S T E E R I N G
O U T P U T B U F F E R S
E
DQs DQPa DQPb DQPc DQPd
E
INPUT REGISTER 1
E
INPUT REGISTER 0
E
OE CE1 CE2 CE3
ZZ
READ LOGIC
SLEEP CONTROL
Cypress Semiconductor Corporation Document #: 38-05558 Rev. *D
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised June 29, 2006
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CY7C1370DV25 CY7C1372DV25
Logic Block Diagram-CY7C1372DV25 (1M x 18)
A0, A1, A MODE
CLK CEN
ADDRESS REGISTER 0
A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC ADV/LD C
C
WRITE ADDRESS REGISTER 1
WRITE ADDRESS REGISTER 2
ADV/LD
BWa
BWb WE
WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC
WRITE DRIVERS
MEMORY ARRAY
S E N S E A M P S
O U T P U T R E G I S T E R S
D A T A S T E E R I N G
O U T P U T B U F F E R S
DQs DQPa DQPb
E
E
INPUT REGISTER 1 E
INPUT REGISTER 0 E
OE CE1 CE2 CE3 ZZ
READ LOGIC
Sleep Control
Selection Guide
250 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 2.6 350 70 200 MHz 3.0 300 70 167 MHz 3.4 275 70 Unit ns mA mA
Document #: 38-05558 Rev. *D
Page 2 of 27
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CY7C1370DV25 CY7C1372DV25
Pin Configurations 100-Pin TQFP Pinout
A A CE1 CE2 BWd BWc BWb BWa CE3 VDD VSS CLK WE CEN OE ADV/LD A A
A A CE1 CE2 NC NC BWb BWa CE3 VDD VSS CLK WE CEN OE ADV/LD A A
NC DQPb NC DQb NC DQb VDDQ VDDQ VSS VSS NC DQb DQb NC DQb DQb DQb DQb VSS VSS VDDQ VDDQ DQb DQb DQb DQb NC VSS VDD NC NC VDD VSS ZZ DQb DQa DQa DQb VDDQ VDDQ VSS VSS DQa DQb DQa DQb DQa DQPb NC DQa VSS VSS VDDQ VDDQ NC DQa DQa NC DQPa NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A A
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPc DQc DQc VDDQ
VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A A
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC
CY7C1370DV25 (512K x 36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
CY7C1372DV25 (1M x 18)
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC(288) NC(144)
NC(288) NC(144)
MODE A A A A A1 A0
NC(36)
MODE A A A A A1 A0
NC(72)
NC(36)
VSS VDD
NC(72)
A A A A A A A
Document #: 38-05558 Rev. *D
VSS VDD
A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Page 3 of 27
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CY7C1370DV25 CY7C1372DV25
Pin Configurations (continued) 119-Ball BGA Pinout
CY7C1370DV25 (512K x 36)
1 A B C D E F G H J K L M N P R T U
VDDQ NC/576M NC/1G DQc DQc VDDQ DQc DQc VDDQ DQd DQd VDDQ DQd DQd NC/144M NC VDDQ
2
A CE2 A DQPc DQc DQc DQc DQc VDD DQd DQd DQd DQd DQPd A NC/72M TMS
3
A A A VSS VSS VSS BWc VSS NC VSS BWd VSS VSS VSS MODE A TDI
4
A ADV/LD VDD NC CE1 OE A WE VDD CLK NC CEN A1 A0 VDD A TCK
5
A A A VSS VSS VSS BWb VSS NC VSS BWa VSS VSS VSS NC A TDO
6
A CE3 A DQPb DQb DQb DQb DQb VDD DQa DQa DQa DQa DQPa A NC/36M NC
7
VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC/288M ZZ VDDQ
CY7C1372DV25 (1M x 18)
1 A B C D E F G H J K L M N P R T U
VDDQ NC/576M NC/1G DQb NC VDDQ NC DQb VDDQ NC DQb VDDQ DQb NC NC/144M NC/72M VDDQ
2
A CE2 A NC DQb NC DQb NC VDD DQb NC DQb NC DQPb A A TMS
3
A A A VSS VSS VSS BWb VSS NC VSS NC VSS VSS VSS MODE A TDI
4
A ADV/LD VDD NC CE1 OE A WE VDD CLK NC CEN A1 A0 VDD NC/36M TCK
5
A A A VSS VSS VSS NC VSS NC VSS BWa VSS VSS VSS NC A TDO
6
A CE3 A DQPa NC DQa NC DQa VDD NC DQa NC DQa NC A A NC
7
VDDQ NC NC NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC/288M ZZ VDDQ
Document #: 38-05558 Rev. *D
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CY7C1370DV25 CY7C1372DV25
Pin Configurations (continued) 165-Ball FBGA Pinout
1 A B C D E F G H J K L M N P R
NC/576M NC/1G DQPc DQc DQc DQc DQc NC DQd DQd DQd DQd DQPd MODE
2
A A NC DQc DQc DQc DQc NC DQd DQd DQd DQd NC NC/36M
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
CY7C1370DV25 (512K x 36) 4 5 6 7
BWc BWd VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
8
ADV/LD
9
A
10
A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A
11
NC NC DQPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DQPa NC/288M A
BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
CE3 CLK
CEN WE
OE
A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
NC/144M NC/72M
A
A
CY7C1372DV25 (1M x 18)
1 A B C D E F G H J K L M N P R
NC/576M NC/1G NC NC NC NC NC NC DQb DQb DQb DQb DQPb MODE
2
A A NC DQb DQb DQb DQb NC NC NC NC NC NC NC/36M
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWb NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
NC BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
6
CE3 CLK
7
CEN WE VSS VSS
8
ADV/LD
9
A
10
A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A
11
A NC DQPa DQa DQa DQa DQa ZZ NC NC NC NC NC NC/288M A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0
OE VSS VDD
A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
NC/144M NC/72M
A
A
Document #: 38-05558 Rev. *D
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CY7C1370DV25 CY7C1372DV25
Pin Definitions
Pin Name A0 A1 A BWa BWb BWc BWd WE ADV/LD I/O Type Pin Description InputAddress Inputs used to select one of the address locations. Sampled at the rising edge of Synchronous the CLK. InputByte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Synchronous Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd. InputWrite Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This Synchronous signal must be asserted LOW to initiate a write sequence. InputAdvance/Load Input used to advance the on-chip address counter or load a new address. Synchronous When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. InputClock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW.
CLK CE1 CE2 CE3 OE
InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with Synchronous CE2 and CE3 to select/deselect the device. InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction Synchronous with CE1 and CE3 to select/deselect the device. InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with Synchronous CE1 and CE2 to select/deselect the device. InputOutput Enable, active LOW. Combined with the synchronous logic block inside the device to Asynchronous control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. InputClock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the Synchronous SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa-DQd are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. I/OBidirectional Data Parity I/O lines. Functionally, these signals are identical to DQs. During write Synchronous sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and DQPd is controlled by BWd. Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order. JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. output Synchronous JTAG serial Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. input Synchronous Test Mode This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. Select Synchronous JTAG-Clock Clock input to the JTAG circuitry.
CEN
DQS
DQPX
MODE
TDO
TDI
TMS
TCK
Document #: 38-05558 Rev. *D
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CY7C1370DV25 CY7C1372DV25
Pin Definitions (continued)
Pin Name VDD VDDQ VSS NC NC/(36M, 72M, 144M, 288M, 576M, 1G) ZZ I/O Type I/O Power Supply Ground - - Power supply for the I/O circuitry. Ground for the device. Should be connected to ground of the system. No connects. This pin is not connected to the die. These pins are not connected. They will be used for expansion to the 36M, 72M, 144M, 288M, 576M, and 1G densities. Pin Description Power Supply Power supply inputs to the core of the device.
InputZZ "Sleep" Input. This active HIGH input places the device in a non-time critical "sleep" Asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output will three-state following the next clock rise. Burst Read Accesses The CY7C1370DV25 and CY7C1372DV25 have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the write signal WE is asserted LOW. The address presented is loaded into the Address Register. The write signals are latched into the Control Logic block. On the subsequent clock rise the data lines are automatically three-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1370DV25 and DQa,b/DQPa,b for CY7C1372DV25). In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted). On the next clock rise the data presented to DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1370DV25 & DQa,b/DQPa,b for CY7C1372DV25) (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete. The data written during the write operation is controlled by BW (BWa,b,c,d for CY7C1370DV25 and BWa,b for CY7C1372DV25) Page 7 of 27
Introduction
Functional Overview The CY7C1370DV25 and CY7C1372DV25 are synchronous-pipelined Burst NoBL SRAMs designed specifically to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.6 ns (250-MHz device). Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BWX can be used to conduct byte write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-MHz device) provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in Document #: 38-05558 Rev. *D
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CY7C1370DV25 CY7C1372DV25
signals. The CY7C1370DV25/CY7C1372DV25 provides byte write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BW) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the CY7C1370DV25 and CY7C1372DV25 are common I/O devices, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1370DV25 and DQa,b/DQPa,b for CY7C1372DV25) inputs. Doing so will three-state the output drivers. As a safety precaution, DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1370DV25 and DQa,b/DQPa,b for CY7C1372DV25) are automatically three-stated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1370DV25/CY7C1372DV25 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four WRITE operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW (BWa,b,c,d for CY7C1370DV25 and BWa,b for CY7C1372DV25) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table (MODE = Floating or VDD)
First Address A1,A0 00 01 10 11 Second Address A1,A0 01 00 11 10 Third Address A1,A0 10 11 00 01 Fourth Address A1,A0 11 10 01 00
Linear Burst Address Table (MODE = GND)
First Address A1,A0 00 01 10 11 Second Address A1,A0 01 10 11 00 Third Address A1,A0 10 11 00 01 Fourth Address A1,A0 11 00 01 10
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ active to sleep current ZZ Inactive to exit sleep current Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min. Max. 80 2tCYC Unit mA ns ns ns ns
Document #: 38-05558 Rev. *D
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CY7C1370DV25 CY7C1372DV25
Truth Table[1, 2, 3, 4, 5, 6, 7]
Operation Deselect Cycle Continue Deselect Cycle Read Cycle (Begin Burst) Read Cycle (Continue Burst) NOP/Dummy Read (Begin Burst) Dummy Read (Continue Burst) Write Cycle (Begin Burst) Write Cycle (Continue Burst) NOP/Write Abort (Begin Burst) Write Abort (Continue Burst) Ignore Clock Edge (Stall) Sleep Mode Address Used None None External Next External Next External Next None Next Current None CE H X L X L X L X L X X X ZZ L L L L L L L L L L L H ADV/LD L H L H L H L H L H X X WE X X H X H X L X L X X X BWx X X X X X X L L H H X X OE X X L L H H X X X X X X L L L L L L L L L L H X CEN CLK L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H X DQ Tri-state Tri-state Data Out (Q) Data Out (Q) Tri-state Tri-state Data In (D) Data In (D) Tri-state Tri-state - Tri-state
Partial Write Cycle
Read Write - No bytes written
Description[1, 2, 3, 8]
WE H L L L L L L L L L L L L L L L L BWd X H H H H H H H H L L L L L L L L BWc X H H H H L L L L H H H H L L L L BWb X H H L L H H L L H H L L H H L L BWa X H L H L H L H L H L H L H L H L
Function (CY7C1370DV25)
Write Byte a - (DQa and DQPa) Write Byte b - (DQb and DQPb) Write Bytes b, a Write Byte c - (DQc and DQPc) Write Bytes c, a Write Bytes c, b Write Bytes c, b, a Write Byte d - (DQd and DQPd) Write Bytes d, a Write Bytes d, b Write Bytes d, b, a Write Bytes d, c Write Bytes d, c, a Write Bytes d, c, b Write All Bytes
Notes: 1. X = "Don't Care", H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details. 2. Write is defined by WE and BWX. See Write Cycle Description table for details. 3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes. 4. The DQ and DQP pins are controlled by the current cycle and the OE signal. 5. CEN = H inserts wait states. 6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQPX = Three-state when OE is inactive or when the device is deselected, and DQs = data when OE is active. 8. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Document #: 38-05558 Rev. *D
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CY7C1370DV25 CY7C1372DV25
Function (CY7C1372DV25) Read Write - No Bytes Written Write Byte a - (DQa and DQPa) Write Byte b - (DQb and DQPb) Write Both Bytes WE H L L L L Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.) Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.) BWb x H H L L BWa x H L H L
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1370DV25/CY7C1372DV25 incorporates a serial boundary scan test access port (TAP).This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels. The CY7C1370DV25/CY7C1372DV25 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device.
TAP Controller State Diagram
1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 1
TAP Controller Block Diagram
0 Bypass Register
210
SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0
0
TDI
1
Selection Circuitry
Instruction Register
31 30 29 . . . 2 1 0
Selection
Circuitry
TDO
Identification Register
0
x. . . . .210
Boundary Scan Register
TCK TMS TAP CONTROLLER
The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Document #: 38-05558 Rev. *D
Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.
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TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted Document #: 38-05558 Rev. *D through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required--that is, while data captured is shifted out, the preloaded data can be shifted in.
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BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST Output Bus Tri-State IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at bit #85 (for 119-BGA package) or bit #89 (for 165-fBGA package). When this scan cell, called the "extest output bus tri-state," is latched into the preload register during the "Update-DR" state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the "Shift-DR" state. During "Update-DR," the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the "Test-Logic-Reset" state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions.
TAP Timing
1 Test Clock (TCK)
tTMSS
2
3
4
5
6
tTH tTMSH
t TL
tCYC
Test Mode Select (TMS)
tTDIS tTDIH
Test Data-In (TDI)
tTDOV tTDOX
Test Data-Out (TDO) DON'T CARE UNDEFINED
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TAP AC Switching Characteristics Over the Operating Range[9, 10]
Parameter Clock tTCYC tTF tTH tTL tTDOV tTDOX tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 5 5 5 ns ns ns TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH time TCK Clock LOW time TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid TMS Set-up to TCK Clock Rise TDI Set-up to TCK Clock Rise Capture Set-up to TCK Rise 0 5 5 5 20 20 10 50 20 ns MHz ns ns ns ns ns ns ns Description Min. Max. Unit
Output Times
Set-up Times
Notes: 9. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
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2.5V TAP AC Test Conditions
Input pulse levels ................................................ VSS to 2.5V Input rise and fall time..................................................... 1 ns Input timing reference levels .........................................1.25V Output reference levels.................................................1.25V Test load termination supply voltage.............................1.25V
2.5V TAP AC Output Load Equivalent
1.25V 50 TDO Z O= 50 20pF
TAP DC Electrical Characteristics And Operating Conditions
(0C < TA < +70C; VDD = 2.5V 0.125V unless otherwise noted)[11] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current GND < VIN < VDDQ Test Conditions IOH = -1.0 mA, VDDQ = 2.5V IOH = -100 A, VDDQ = 2.5V IOL = 8.0 mA, VDDQ = 2.5V IOL = 100 A VDDQ = 2.5V VDDQ = 2.5V VDDQ = 2.5V 1.7 -0.3 -5 Min. 2.0 2.1 0.4 0.2 VDD + 0.3 0.7 5 Max. Unit V V V V V V A
Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan Order (119-ball BGA package) Boundary Scan Order (165-ball fBGA package) Bit Size (x18) 3 1 32 85 89 Bit Size (x36) 3 1 32 85 89
Identification Register Definitions
Instruction Field Revision Number (31:29) Cypress Device ID (28:12) Cypress JEDEC ID (11:1) ID Register Presence (0) CY7C1372DV25 000 01011001000100101 00000110100 1 CY7C1370DV25 000 01011001000010101 00000110100 1 Description Reserved for version number. Reserved for future use. Allows unique identification of SRAM vendor. Indicate the presence of an ID register.
Note: 11.All voltages referenced to VSS (GND).
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Identification Codes
Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Description Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations.
119-Ball BGA Boundary Scan Order [12, 13]
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Ball ID H4 T4 T5 T6 R5 L5 R6 U6 R7 T7 P6 N7 M6 L7 K6 P7 N6 L6 K7 J5 H6 G7 Bit # 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Ball ID F6 E7 D7 H7 G6 E6 D6 C7 B7 C6 A6 C5 B5 G5 B6 D4 B4 F4 M4 A5 K4 E4 Bit # 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Ball ID G4 A4 G3 C3 B2 B3 A3 C2 A2 B1 C1 D2 E1 F2 G1 H2 D1 E2 G2 H1 J3 2K Bit # 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 Ball ID L1 M2 N1 P1 K1 L2 N2 P2 R3 T1 R1 T2 L3 R2 T3 L4 N4 P4 Internal
Notes: 12. Balls which are NC (No Connect) are pre-set LOW. 13. Bit# 85 is pre-set HIGH.
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165-Ball FBGA Boundary Scan Order [12, 14]
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Note: 14. Bit# 89 is pre-set HIGH.
Ball ID N6 N7 N10 P11 P8 R8 R9 P9 P10 R10 R11 H11 N11 M11 L11 K11 J11 M10 L10 K10 J10 H9 H10 G11 F11 E11 D11 G10 F10 E10
Bit # 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Ball ID D10 C11 A11 B11 A10 B10 A9 B9 C10 A8 B8 A7 B7 B6 A6 B5 A5 A4 B4 B3 A3 A2 B2 C2 B1 A1 C1 D1 E1 F1
Bit # 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89
Ball ID G1 D2 E2 F2 G2 H1 H3 J1 K1 L1 M1 J2 K2 L2 M2 N1 N2 P1 R1 R2 P3 R3 P2 R4 P4 N5 P6 R6 Internal
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VDD Relative to GND........ -0.5V to +3.6V Supply Voltage on VDDQ Relative to GND ...... -0.5V to +VDD DC to Outputs in Tri-State ................... -0.5V to VDDQ + 0.5V Range Commercial Industrial DC Input Voltage ................................... -0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Ambient Temperature 0C to +70C -40C to +85C VDD/VDDQ 2.5V 5%
Electrical Characteristics Over the Operating Range[15, 16]
Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[17] Input LOW Voltage[17] Input Leakage Current except ZZ and MODE for 2.5V I/O for 2.5V I/O, IOH = -1.0 mA for 2.5V I/O, IOL= 1.0 mA for 2.5V I/O for 2.5V I/O GND VI VDDQ 1.7 -0.3 -5 -30 5 -5 30 -5 4.0-ns cycle, 250 MHz 5.0-ns cycle, 200 MHz 6.0-ns cycle, 167 MHz ISB1 Automatic CE Power-down Current--TTL Inputs Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz VIN VIH or VIN VIL, f = fMAX = 5.0-ns cycle, 200 MHz 1/tCYC 6.0-ns cycle, 167 MHz 5 350 300 275 160 150 140 70 Test Conditions Min. 2.375 2.375 2.0 0.4 VDD + 0.3V 0.7 5 Max. 2.625 VDD Unit V V V V V V A A A A A A mA mA mA mA mA mA mA
Input Current of MODE Input = VSS Input = VDD Input Current of ZZ IOZ IDD Input = VSS Input = VDD Output Leakage Current GND VI VDD, Output Disabled VDD Operating Supply VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC
ISB2
Automatic CE Max. VDD, Device Deselected, All speed grades Power-down VIN 0.3V or VIN > VDDQ - 0.3V, Current--CMOS Inputs f = 0 Automatic CE Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz Power-down VIN 0.3V or VIN > VDDQ - 0.3V, 5.0-ns cycle, 200 MHz Current--CMOS Inputs f = fMAX = 1/tCYC 6.0-ns cycle, 167 MHz Automatic CE Power-down Current--TTL Inputs Max. VDD, Device Deselected, VIN VIH or VIN VIL, f = 0 All speed grades
ISB3
135 130 125 80
mA mA mA mA
ISB4
Notes: 15. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> -2V (Pulse width less than tCYC/2). 16. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 17. Tested initially and after any design or process change that may affect these parameters.
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Capacitance[17]
Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 2.5V. VDDQ = 2.5V 100 TQFP Package 5 5 5 119 BGA Package 8 8 8 165 FBGA Package 9 9 9 Unit pF pF pF
Thermal Resistance[17]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 100 TQFP Package 28.66 4.08 119 BGA Package 23.8 6.2 165 FBGA Package 20.7 4.0 Unit C/W C/W
AC Test Loads and Waveforms
2.5V I/O Test Load
OUTPUT Z0 = 50 2.5V OUTPUT RL = 50 5 pF R = 1538 VT = 1.25V INCLUDING JIG AND SCOPE R = 1667 VDDQ 10% GND 1 ns ALL INPUT PULSES 90% 90% 10% 1 ns
(a)
(b)
(c)
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Switching Characteristics Over the Operating Range
Parameter tPower tCYC FMAX tCH tCL Output Times tCO tEOV tDOH tCHZ tCLZ tEOHZ tEOLZ Set-up Times tAS tDS tCENS tWES tALS tCES Hold Times tAH tDH tCENH tWEH tALH tCEH Address Hold After CLK Rise Data Input Hold After CLK Rise CEN Hold After CLK Rise WE, BWx Hold After CLK Rise ADV/LD Hold after CLK Rise Chip Select Hold After CLK Rise 0.3 0.3 0.3 0.3 0.3 0.3 0.4 0.4 0.4 0.4 0.4 0.4 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns Address Set-up Before CLK Rise Data Input Set-up Before CLK Rise CEN Set-up Before CLK Rise WE, BWx Set-up Before CLK Rise ADV/LD Set-up Before CLK Rise Chip Select Set-up 1.2 1.2 1.2 1.2 1.2 1.2 1.4 1.4 1.4 1.4 1.4 1.4 1.5 1.5 1.5 1.5 1.5 1.5 ns ns ns ns ns ns Data Output Valid After CLK Rise OE LOW to Output Valid Data Output Hold After CLK Rise Clock to High-Z[19, 20, 21] 1.0 2.6 0 0 High-Z[19, 20, 21] Low-Z[19, 20, 21] Clock to Low-Z[19, 20, 21] OE HIGH to Output OE LOW to Output 1.0 2.6 1.3 3.0 0 2.6 2.6 1.3 3.0 1.3 3.4 3.0 3.0 1.3 3.4 3.4 3.4 ns ns ns ns ns ns ns
[18] [22, 23]
-250 Description VCC (typical) to the first access read or write Clock Cycle Time Maximum Operating Frequency Clock HIGH Clock LOW 1.7 1.7 Min. 1 4.0 250 2.0 2.0 Max. 1 5
-200 Min. Max. 1 6 200
-167 Min. Max. Unit ms ns 167 2.2 2.2 MHz ns ns
Clock
Notes: 18. This part has a voltage regulator internally; tPower is the time power needs to be supplied above VDD minimum initially, before a Read or Write operation can be initiated. 19. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 20. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 21. This parameter is sampled and not 100% tested. 22. Timing reference 1.25V when VDDQ = 2.5V. 23. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
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Switching Waveforms
Read/Write/Timing[24, 25, 26]
1 CLK
tCENS tCENH
2
t CYC
3
4
5
6
7
8
9
10
tCH
tCL
CEN
tCES tCEH
CE ADV/LD WE BWx ADDRESS
tAS
A1
tAH
A2
tDS tDH
A3
A4
tCO tCLZ tDOH
A5
tOEV
A6
tCHZ
A7
Data In-Out (DQ)
D(A1)
D(A2)
D(A2+1)
Q(A3)
Q(A4)
tOEHZ
Q(A4+1)
D(A5)
Q(A6)
tDOH
OE
WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) BURST READ Q(A4+1) WRITE D(A5)
tOELZ
READ Q(A6)
WRITE D(A7)
DESELECT
DON'T CARE
UNDEFINED
Notes: 24. For this waveform ZZ is tied LOW. 25. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 26. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
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Switching Waveforms (continued)
NOP,STALL and DESELECT Cycles[24, 25, 27]
1
CLK CEN CE ADV/LD WE BWx ADDRESS A1
2
3
4
5
6
7
8
9
10
A2
A3
A4
A5
tCHZ
Data In-Out (DQ)
WRITE D(A1) READ Q(A2) STALL
D(A1)
Q(A2)
Q(A3)
D(A4)
Q(A5)
READ Q(A3)
WRITE D(A4)
STALL
NOP
READ Q(A5)
DESELECT
CONTINUE DESELECT
DON'T CARE
UNDEFINED
ZZ Mode Timing[28, 29]
CLK
t ZZ t ZZREC
ZZ
t ZZI
I
SUPPLY I DDZZ t RZZI DESELECT or READ Only
ALL INPUTS (except ZZ)
Outputs (Q)
High-Z
DON'T CARE
Notes: 27. The Ignore Clock Edge or Stall cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle 28. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 29. I/Os are in High-Z when exiting ZZ sleep mode.
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CY7C1370DV25 CY7C1372DV25
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 167 Ordering Code CY7C1370DV25-167AXC CY7C1372DV25-167AXC CY7C1370DV25-167BGC CY7C1372DV25-167BGC CY7C1370DV25-167BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1372DV25-167BGXC CY7C1370DV25-167BZC CY7C1372DV25-167BZC CY7C1370DV25-167BZXC CY7C1372DV25-167BZXC CY7C1370DV25-167AXI CY7C1372DV25-167AXI CY7C1370DV25-167BGI CY7C1372DV25-167BGI CY7C1370DV25-167BGXI CY7C1372DV25-167BGXI CY7C1370DV25-167BZI CY7C1372DV25-167BZI CY7C1370DV25-167BZXI CY7C1372DV25-167BZXI 200 CY7C1370DV25-200AXC CY7C1372DV25-200AXC CY7C1370DV25-200BGC CY7C1372DV25-200BGC CY7C1370DV25-200BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1372DV25-200BGXC CY7C1370DV25-200BZC CY7C1372DV25-200BZC CY7C1370DV25-200BZXC CY7C1372DV25-200BZXC CY7C1370DV25-200AXI CY7C1372DV25-200AXI CY7C1370DV25-200BGI CY7C1372DV25-200BGI CY7C1370DV25-200BGXI CY7C1372DV25-200BGXI CY7C1370DV25-200BZI CY7C1372DV25-200BZI CY7C1370DV25-200BZXI CY7C1372DV25-200BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Package Diagram Part and Package Type Operating Range Commercial
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Document #: 38-05558 Rev. *D
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CY7C1370DV25 CY7C1372DV25
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. 250 CY7C1370DV25-250AXC CY7C1372DV25-250AXC CY7C1370DV25-250BGC CY7C1372DV25-250BGC CY7C1370DV25-250BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1372DV25-250BGXC CY7C1370DV25-250BZC CY7C1372DV25-250BZC CY7C1370DV25-250BZXC CY7C1372DV25-250BZXC CY7C1370DV25-250AXI CY7C1372DV25-250AXI CY7C1370DV25-250BGI CY7C1372DV25-250BGI CY7C1370DV25-250BGXI CY7C1372DV25-250BGXI CY7C1370DV25-250BZI CY7C1372DV25-250BZI CY7C1370DV25-250BZXI CY7C1372DV25-250BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
Document #: 38-05558 Rev. *D
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CY7C1370DV25 CY7C1372DV25
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050)
16.000.20 14.000.10
100 1 81 80
1.400.05
0.300.08
22.000.20
20.000.10
0.65 TYP.
30 31 50 51
121 (8X)
SEE DETAIL
A
0.20 MAX. 1.60 MAX. 0 MIN. SEATING PLANE 0.25 GAUGE PLANE STAND-OFF 0.05 MIN. 0.15 MAX.
NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS
0-7
R 0.08 MIN. 0.20 MAX.
0.600.15 0.20 MIN. 1.00 REF.
DETAIL
51-85050-*B
A
Document #: 38-05558 Rev. *D
0.10
R 0.08 MIN. 0.20 MAX.
Page 24 of 27
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CY7C1370DV25 CY7C1372DV25
Package Diagrams (continued)
119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)
51-85115-*B
Document #: 38-05558 Rev. *D
Page 25 of 27
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CY7C1370DV25 CY7C1372DV25
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)
TOP VIEW TOP VIEW BOTTOM VIEW BOTTOM VIEW PIN 1 CORNER PIN 1 CORNER O0.05 M C O0.05 M C O0.25 M C A B O0.25 M C A B -0.06 O0.50 (165X) -0.06 O0.50 (165X) +0.14
3
PIN 1 CORNER PIN 1 CORNER
1 A B C D E F G
A B
2
1
3
2
4
5
4
6
5
7
6
8
7
9
10 8
11 9 10
11
11
10
9 11
8 10
9
7
6 8
5 7
6
4
5
3
+0.14 2 4
3
1
2
1 A
A B C D E F G H J K L M N P R
B
1.00
C D E F
1.00
C D E F G
15.000.10
15.000.10
14.00 15.000.10
G H J K
15.000.10
H J K L M N P R
14.00
H J K
7.00
7.00
L M N P R
L M N P R
A
A
A
A
5.00
1.00
5.00
1.00
10.00 B 13.000.10 13.000.10 B 0.15(4X)
10.00
B
B 0.15(4X)
13.000.10 13.000.10
1.40 MAX.
NOTESNOTES : : SOLDER PAD TYPE : TYPE : NON-SOLDER MASK DEFINED (NSMD) SOLDER PAD NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0.475g0.475g PACKAGE WEIGHT : JEDEC JEDEC REFERENCE : MO-216 / DESIGN 4.6C REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE CODE : BB0AC PACKAGE : BB0AC
51-85180-*A 51-85180-*A
0.530.05 0.25 C
1.40 MAX.
0.25 C
0.530.05
0.15 C
0.36
0.36
C
SEATINGSEATING PLANE PLANE C 0.350.06 0.350.06
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05558 Rev. *D
0.15 C
Page 26 of 27
(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1370DV25 CY7C1372DV25
Document History Page
Document Title: CY7C1370DV25/CY7C1372DV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBLTM Architecture Document Number: 38-05558 REV. ** *A ECN No. 254509 288531 Issue Date See ECN See ECN Orig. of Change RKF SYT New data sheet Edited description under "IEEE 1149.1 Serial Boundary Scan (JTAG)" for non-compliance with 1149.1 Removed 225 Mhz Speed Bin Added lead-free information for 100-Pin TQFP, 119 BGA and 165 FBGA package Added comment of `Lead-free BG packages availability' below the Ordering Information Address expansion pins/balls in the pinouts for all packages are modified as per JEDEC standard Added description on EXTEST Output Bus Tri-State Changed description on the Tap Instruction Set Overview and Extest Changed JA and JC for TQFP Package from 31 and 6 C/W to 28.66 and 4.08 C/W respectively Changed JA and JC for BGA Package from 45 and 7 C/W to 23.8 and 6.2 C/W respectively Changed JA and JC for FBGA Package from 46 and 3 C/W to 20.7 and 4.0 C/W respectively Modified VOL, VOH test conditions Removed comment of `Lead-free BG packages availability' below the Ordering Information Updated Ordering Information Table Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Changed the description of IX from Input Load Current to Input Leakage Current on page# 18 Changed the IX current values of MODE on page # 18 from -5 A and 30 A to -30 A and 5 A Changed the IX current values of ZZ on page # 18 from -30 A and 5 A to -5 A and 30 A Changed VIH < VDD to VIH < VDDon page # 18 Updated Ordering Information Table Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND. Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table. Description of Change
*B
326078
See ECN
PCI
*C
418125
See ECN
NXR
*D
475677
See ECN
VKN
Document #: 38-05558 Rev. *D
Page 27 of 27
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